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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
INTRODUCTION
S6A0073 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1, 2 or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
* * * * * * * * * * * * Character type dot matrix LCD driver & controller Internal driver : 34 common and 60 segment signal output Easy interface with 4-bit or 8-bit MPU Clock synchronized serial Interface 5 x 8 or 6 x 8 dots matrix possible Extension driver interface possible Bi-directional shift function All character reverse display Display shift per line Voltage converter for LCD drive voltage : 13V max (2 times / 3 times) Various instruction functions Automatic power on reset
FEATURES
* Internal Memory - Character Generator ROM (CGROM) : 9,600 bits (240 characters x 5 x 8 dot) - Character Generator RAM (CGRAM) : 64 x 8 bits (8 characters x 5 x 8 dot) - Segment Icon RAM (SEGRAM) : 16 x 8 bits (96 icons max.) - Display Data RAM (DDRAM) : 80 x 8 bits (80 characters max.) * Low power operation - Power supply voltage range: 2.7 to 5.5V (VDD) - LCD Drive voltage range: 3.0 to 13.0V (VDD - V5) * * * * * CMOS process Programmable duty cycle : 1/17, 1/33 (refer to Table 1) Internal oscillator with an external resistor Low power consumption TCP or bare chip available
1
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 1. Programmable Duty Cycles 1) 5-dot Font Width Display Line Numbers 1 2 4 1/17 1/33 1/33 Duty Ratio Single-chip Operation Displayable characters 1 line of 24 characters 2 lines of 24 characters 4 lines of 12 characters Possible icons 60 60 60 With Extension Driver Displayable characters 1 line of 52 characters 2 lines of 32 characters 4 lines of 20 characters 80 80 80 Possible icons
2) 6-dot Font Width Display Line Numbers 1 2 4 1/17 1/33 1/33 Duty Ratio Single-chip Operation Displayable characters 1 line of 20 characters 2 lines of 20 characters 4 lines of 10 characters 60 60 60 Possible icons With Extension Driver Displayable characters 1 line of 50 characters 2 lines of 30 characters 4 lines of 20 characters 96 96 96 Possible icons
2
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
BLOCK DIAGRAM
IE OSC1 OSC2
EXT
Power on Reset (POR) RESET IM RS/ CS E/ SCLK RW/SID
Oscillator Timing Generator CLK1 CLK2 M
7 System Interface Serial 4-bit 8-bit 8 Instruction Register (IR) Instruction Decoder Display Data RAM (DDRAM) 80 x 8-bit 34-bit Shift Register COM0Common COM33 Driver
Address Counter
7 7 8 8 Input/ Output Buffer Busy Flag DB0-SOD 3 7 8 8 LCD Driver Voltage Selector Data Register (DR) 8 8 SEG1Segment SEG60 Driver D
DB4-DB7 DB3-DB1
60-bit Shift Register
60-bit Latch Circuit
Vci C1 C2 V5OUT2 V5OUT3 VDD GND(VSS) Voltage Converter
Segment ICONRAM (SEGRAM) 16 bytes
Character Generator RAM (CGRAM) 64 bytes
Character Generator ROM (CGROM) 9600 bits 5
Cursor & Blink Controller
V1 - V5
5/6 Parallel to Serial Converter and Smooth Scroll Circuit
3
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CONFIGURATION
SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 VDD OSC2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101
SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
Y
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 (0,0) X 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 V1 V2
CHIP SIZE: 4870 x 5770 PAD SIZE: 100 x 100 UNIT: m
4
OSC1 CLK1 CLK2 D M RESET IM EXT IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vci C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
PAD CENTER COORDINATES
PAD NUM. PAD NAME COORDINATE X Y PAD NUM. PAD NAME COORDINATE X Y PAD NUM. PAD NAME COORDINATE X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31
-1687 -1812 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269 -2269
2719 2719 2122 1997 1872 1747 1622 1497 1372 1247 1122 997 872 747 622 497 372 134 9 -116 -241 -366 -491 -616 -741 -866 -991 -1116 -1241 -1366 -1491 -1616
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
EXT IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vci C2 C1 VSS2 V5OUT2 V5OUR3 V5 V4 V3 V2 V1 COM24 COM23 COM22 COM21 COM20 COM19 COM18
-986 -861 -736 -611 -486 -361 -236 -111 14 139 264 389 514 639 764 889 1014 1139 1264 1389 1514 1639 1764 2269 2269 2269 2269 2269 2269 2269 2269 2269
-2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2719 -2116 -1991 -1866 -1741 -1616 -1491 -1366 -1241 -1116
87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33
2269 2269 2269 2269 2269 2269 2269 2269 2269 2269 2269 2269 2269 2269 1813 1688 1563 1438 1313 1188 1063 938 813 688 563 438 313 188 63 -62 -187 -312
497 622 747 872 997 1122 1247 1372 1497 1622 1747 1872 1997 2122 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719 2719
5
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES (Continued)
PAD NUM. PAD NAME COORDINATE X Y PAD NUM. PAD NAME COORDINATE X Y PAD NUM. PAD NAME COORDINATE X Y
33 34 35 36 37 38 39 40 41 42 43
COM32 COM33 VDD OSC2 OSC1 CLK1 CLK2 D M RESET IM
-2269 -2269 -2269 -2269 -1861 -1736 -1611 -1486 -1361 -1236 -1111
-1741 -1866 -1991 -2116 -2719 -2719 -2719 -2719 -2719 -2719 -2719
76 77 78 79 80 81 82 83 84 85 86
COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG1
2269 2269 2269 2269 2269 2269 2269 2269 2269 2269 2269
-991 -866 -741 -616 -491 -366 -241 -116 9 134 372
119 120 121 122 123 124 125 126 127 128
SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43
-437 -562 -687 -812 -937 -1062 -1187 -1312 -1437 -1562
2719 2719 2719 2719 2719 2719 2719 2719 2719 2719
6
NC VDD OSC2 OSC1 CLK1 CLK2 D M RESET IM EXT IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vci C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 NC
TCP OUTLINE
PIN CONFIGURATION OF TCP
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
OUTPUT SIDE
S6A0073
S6A0073
7
8
NC NC COM33
NC
S6A0073
VDD
OSC2
OSC1
CLK1
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK2
D
...
M
RESET
IM
COM9 SEG60
EXT
IE
VSS1
RS/CS
RW/SID
E/SCLK
DB0/SOD
DB1
......
DB2
DB3
DB4
S6A0073 PAD DIAGRAM 134-TCP-35mm
DB5
DB6
DB7
Vci
C2
C1
SEG1 COM0
VSS2
V5OUT2
...
V5OUT3
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86
2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101
85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
V5
V4
COM24 NC NC
V3
V2
V1
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
NC
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
PIN DESCRIPTION
Pin (No) VDD(35) VSS1, VSS2 (46, 61) V1-V5 (68 - 64) Vci (58) I Power supply I/O Name 0V (GND) Bias voltage level for LCD driving Input voltage to the voltage converter to generate LCD drive voltage (Vci = 1.0 to 4.5V). Segment output Common output Oscillator Segment signal output for LCD drive. Common signal output for LCD drive When using internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. When EXT = "High", each outputs latch clock and shift clock for extension driver. To use the voltage converter (2 times /3 times), these pins must be connected to the external capacitance. When EXT = "High", outputs the alternating signal to convert LCD driver waveform to AC for Extension driver. When EXT = "High", outputs extension driver data (the 61th dot's data) When EXT = "High", makes extension driver control signal enable, When EXT = "Low", suppress extra current consumption and CLK1,CLK2,M,D should be open. Initialized to Low When IE = "High", instruction set is selected as Table 6. When IE = "Low", instruction set is selected as Table 10. LCD LCD External resistor/oscilla tor (OSC1) Extension driver External capacitance Extension driver Extension driver Description for logical circuit (+3V, +5V) Power Supply Interface
SEG1 - SEG60 (86 -128, 1- 17) COM0 - COM33 (85 - 69, 18 - 34) OSC1, OSC2 (37, 36)
O O I(OSC1), O(OSC2)
CLK1, CLK2 (38, 39) C1, C2 (60, 59) M (41)
O I
Latch (CLK1)/ Shift (CLK2) clock External capacitance input Alternated signal for LCD driver output Display data interface Extension driver control signal
O
D(40) EXT(44)
O I
RESET (42) IE (45)
I I
Reset pin Selection pin of instruction set.
-
9
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PIN DESCRIPTION (continued)
Pin(No) V5OUT2 (62) I/O O Name Two times converter output Description The value of Vci is converted two times. To use three times converter, the same capacitance as that of C1-C2 should be connected here. The value of Vci is converted three times. Select Interface mode with the MPU. When IM = "Low" : serial mode, When IM = "High" : 4-bit/8-bit bus mode. When bus mode, used as register selection input. When RS/CS = "High", Data register is selected. When RS/CS = "Low", Instruction register is selected. In serial mode, used as chip selection input. When RS/CS = "Low", selected. When RS/CS = "High", not selected.(Low access enable) RW/SID (48) I Read, write /Serial input data In bus mode, used as read/write selection input. When RW/SID = "High", read operation When RW/SID = "Low", write operation. In serial mode, used for data input pin. When bus mode, used as read, write enable signal. When serial mode, used as serial clock input pin. DB0/SOD (50) I/O, O Data bus 0 bit /Serial output data In 8-bit bus mode, used as lowest bidirectional data bit. During 4-bit bus mode, Open this pin. In serial mode, used as serial data output pin. If not in read operation, open this pin. DB1 - DB3 (51 - 53) I/O Data bus 1- 7 In 8-bit bus mode, used as low order bidirectional data bus. During 4-bit bus mode or serial mode, open these pins. DB4 - DB7 (54 - 57) In 8-bit bus mode, used as high order bidirectional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 used for Busy Flag output. During serial mode, open these pins. MPU MPU MPU MPU Interface V5 / capacitance
V5OUT3 (63) IM (43) I
Three times converter output Interface mode selection Register select /Chip select
V5 -
RS/CS (47)
I
MPU
E/SCLK (49)
I
Read, write enable /Serial clock
MPU
10
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
FUNCTION DESCRIPTION
System Interface This chip has all three kinds of interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit) are selected by IM input, and 4-bit bus and 8-bit bus are selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low"). Table 2. Various Kinds of Operations according to RS and R/W Bits RS L L H H R/W L H L H Operation Instruction Write operation (MPU writes Instruction code into IR) Read Busy flag(DB7) and address counter (DB0 - DB6) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR)
Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7. Before executing the next instruction, be sure that BF is not High.
Display Data RAM (DDRAM) DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSB AC6 AC5 AC4 AC3 AC2 AC1
LSB AC0
Figure 1. DDRAM Address
11
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
1) Display of 5-dot Font Width Character (1) 5-dot 1-line Display In case of 1 line display with 5-dot font, the address range of DDRAM is 00H - 4FH (refer to Figure 2). When EXT = "High", extension driver will be used. Figure 3 shows the example that 40 segment extension driver is added
Display position 1 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B 13 0C SEG1 14 0D 15 0E 16 0F 17 10 18 11 19 12 20 13 21 14 22 15 23 16 24 17
COM1 00 COM8
SEG1
COM9 COM16
S6A0073
SEG60
S6A0073 DDRAM Address
SEG60
1
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11 0B
12 0C
13 0D
14 0E
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
COM1 01 COM8
1
COM9 COM16
(After Shift Left) 2 00 3 01 4 02 5 03 6 04 7 05 8 06 9 07 10 08 11 09 12 0A 13 0B 14 0C 15 0D 16 0E 17 0F 18 10 19 11 20 12 21 13 22 14 23 15 24 16
COM1 4F COM8
COM9 COM16
(After Shift Right)
Figure 2. 1-line x 24ch. Display (5-dot font width)
1 COM1 COM8
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30 31
32 COM9 COM16
00 01 02 03 04 05 06 07 08 09 0A 0B
SEG1 S6A0073 SEG60
0C 0D 0E 0F 10 11 12 13 14 15 16 17
SEG1 S6A0073 SEG60
18 19 1A 1B 1C 1D 1E 1F
SEG1 Extension Driver (40SEG) SEG40
1 COM1 COM8
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30 31
32 COM9 COM16
01 02 03 04 05 06 07 08 09 0A 0B 0C
0D 0E 0F 10 11 12 13 14 15 16 17 18 (After Shift Left)
19 1A 1B 1C 1D 1E 1F 20
1 COM1 COM8
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30 31
32 COM9 COM16
4F 00 01 02 03 04 05 06 07 08 09 0A
0B 0C 0D 0E 0F 10 11 12 13 14 15 16 (After Shift Right)
17 18 19 1A 1B 1C 1D 1E
Figure 3. 1-line x 32ch. Display with 40 SEG. extension driver (5-dot font width)
12
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
(2) 5-dot 2-line Display In case of 2 line display with 5-dot font, the address range of DDRAM is 00H - 27H,40H - 67H (refer to Figure 4). When EXT = "High", extension driver will be used. Figure 5 shows the example that 40 segment extension driver is added.
Display position 1 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B 13 14 15 16 0F 17 10 18 11 19 12 20 13 21 14 22 15 23 16 24 17
COM1 COM8 COM17 COM24
00
0C 0D 0E
COM9 COM16 COM25 COM32
DDRAM Address 40 SEG1 1 2 02 3 03 4 04 5 05 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E SEG1 13 14 15 0F 16 10 17 11 4F 50 51 52 53 54 55 56 57
S6A0073 6 06 7 07 8 08 9 09 10 0A
SEG60 11 0B 12 0C
S6A0073 18 12 19 13 20 14 21 15 22 16
SEG60 23 17 24 18
COM1 01 COM8 COM17 COM24
41
0D 0E
COM9 COM16
42
43
44
45
46
47
48
49
4A
4B
4C
4D 4E
4F
50
51
52
53
54
55
56
57
58
COM25 COM32
(After Shift Left) 1 2 00 3 01 4 02 5 03 6 04 7 05 8 06 9 07 10 08 11 09 12 0A 13 0B 14 15 16 17 0F 18 10 19 11 20 12 21 13 22 14 23 15 24 16
COM1 27 COM8 COM17 COM24
67
0C 0D 0E
COM9 COM16 COM25 COM32
40
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D 4E
4F
50
51
52
53
54
55
56
(After Shift Right)
Figure 4. 2-line x 24ch. Display (5-dot Font Width)
1 COM1 COM8 COM17 COM24
2
3
4
5
6
7
8
9
10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32
00 01 02 03 04 05 06 07 08 09 0A 0B 40 41 42 43 44 45 46 47 48 49 4A 4B
SEG1 S6A0073 SEG60
0C 0D 0E 0F 10 11 12 13 14 15 16 17 4C 4D 4E 4F 50 51 52 53 54 55 56 57
SEG1 S6A0073 SEG60
18 19 1A 1B 1C 1D 1E 1F 58 59 5A 5B 5C 5D 5E 5F
SEG1 Extension Driver (40SEG) SEG40
COM9 COM16 COM25 COM32
1 COM1 COM8 COM17 COM24
2
3
4
5
6
7
8
9
10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32 COM9
01 02 03 04 05 06 07 08 09 0A 0B 0C 41 42 43 44 45 46 47 48 49 4A 4B 4C
0D 0E 0F 10 11 12 13 14 15 16 17 18 4D 4E 4F 50 51 52 53 54 55 56 57 58 (After Shift Left)
19 1A 1B 1C 1D 1E 1F 20 59 5A 5B 5C 5D 5E 5F 60
COM16 COM25 COM32
1 COM1 COM8 COM17 COM24
2
3
4
5
6
7
8
9
10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32 COM9
4F 00 01 02 03 04 05 06 07 08 09 0A 67 40 41 42 43 44 45 46 47 48 49 4A
0B 0C 0D 0E 0F 10 11 12 13 14 15 16 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 (After Shift Right)
17 18 19 1A 1B 1C 1D 1E 57 58 59 5A 5B 5C 5D 5E
COM16 COM25 COM32
Figure 5. 2-line x 32ch. Display with 40 SEG. Extension Driver (5-dot Font Width)
13
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(3) 5-dot 4-line Display In case of 4 line display with 5-dot font, the address range of DDARM is 00H - 13H, 20H - 33H, 40H - 53H, 60H 73H (refer to Figure 6). When EXT = "High", extension driver will be used. Figure 7 shows the example that 40 segment extension driver is added.
1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 00 20 40 60 SEG1 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 01 21 41 61
2 01 21 41 61
3 02 22 42 62
4 03 23 43 63
5 04 24 44 64
6 05 25 45 65
7 06 26 46 66
8 07 27 47 67
9 08 28 48 68
10 09 29 49 69
11 0A 2A 4A 6A
12 0B 2B 4B 6B
Display position DDRAM Address
S6A0073 2 02 22 42 62 3 03 23 43 63 4 04 24 44 64 5 05 25 45 65 6 06 26 46 66 7 07 27 47 67 8 08 28 48 68 9 09 29 49 69 10 0A 2A 4A 6A
SEG60 11 0B 2B 4B 6B 12 0C 2C 4C 6C
(After Shift Left) 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 13 33 53 73 2 00 20 40 60 3 01 21 41 61 4 02 22 42 62 5 03 23 43 63 6 04 24 44 64 7 05 25 45 65 8 06 26 46 66 9 07 27 47 67 10 08 28 48 68 11 09 29 49 69 12 0A 2A 4A 6A
(After Shift Right)
Figure 6. 4-line x 12ch. Display (5-dot Font Width)
14
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 00 20 40 60 SEG1 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 01 21 41 61
2 01 21 41 61
3 02 22 42 62
4 03 23 43 63
5 04 24 44 64
6 05 25 45 65
7 06 26 46 66
8 07 27 47 67
9 08 28 48 68
10 09 29 49 69
11 0A 2A 4A 6A
12 0B 2B 4B 6B
13 0C 2C 4C 6C
14 0D 2D 4D 6D
15 0E 2E 4E 6E
16 0F 2F 4F 6F
17 10 30 50 70
18 11 31 51 71
19 12 32 52 72
20 13 33 53 73
Display position DDRAM Address
S6A0073 2 02 22 42 62 3 03 23 43 63 4 04 24 44 64 5 05 25 45 65 6 06 26 46 66 7 07 27 47 67 8 08 28 48 68 9 09 29 49 69 10 0A 2A 4A 6A
SEG60 11 0B 2B 4B 6B 12 0C 2C 4C 6C
SEG1 13 0D 2D 4D 6D 14 0E 2E 4E 6E 15 0F 2F 4F 6F 16 10 30 50 70
SEG40 Extension Driver (40SEG) 17 11 31 51 71 18 12 32 52 72 19 13 33 53 73 20 00 20 40 60
(After Shift Left) 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 13 33 53 73 2 00 20 40 60 3 01 21 41 61 4 02 22 42 62 5 03 23 43 63 6 04 24 44 64 7 05 25 45 65 8 06 26 46 66 9 07 27 47 67 10 08 28 48 68 11 09 29 49 69 12 0A 2A 4A 6A 13 0B 2B 4B 6B 14 0C 2C 4C 6C 15 0D 2D 4D 6D 16 0E 2E 4E 6E 17 0F 2F 4F 6F 18 10 30 50 70 19 11 31 51 71 20 12 32 52 72
(After Shift Right)
Figure 7. 4-line x 20ch. Display with 40 SEG. Extension Driver (5-dot Font Width)
15
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
2) Display of 6-dot Font Width Character (1) 6-dot 1-line Display In case of 1 line display with 6-dot font, the address range of DDRAM is 00H - 4FH (refer to Figure 8). When EXT = "High", extension driver will be used. Figure 9 shows the example that 40 segment extension driver is added.
1 COM1 COM8 00 SEG1 COM1 COM8
2 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
10 09
11 0A
12 0B
13 0C
14 0D
15 0E
16 0F
17 10
S6A0073
SEG60
SEG1
S6A0073
Display position 18 19 20 COM9 11 12 13 COM16 SEG60 DDRAM Address 12 13 14 COM9 COM16 COM9 COM16
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
(After Shift Left) COM1 COM8 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
(After Shift Right)
Figure 8. 1-line x 20ch. Display (6-dot Font Width)
1 COM1 COM8 00 SEG1
2 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
10 09
11 0A SEG1
12 0B
13 0C
14 0D
15 0E
16 0F
17 10
18 11
19 12
20 13
21 14 SEG1
22 15
23 16
24 17
25 18
26 19 COM9 COM16
S6A0073
SEG60
S6A0073
SEG60
SEG36
Extension Driver (40SEG) 1 COM1 COM8 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26 1A COM9 COM16
(After Shift Left) 1 COM1 COM8 4F 2 00 3 01 4 02 5 03 6 04 7 05 8 06 9 07 10 08 11 09 12 0A 13 0B 14 0C 15 0D 16 0E 17 0F 18 10 19 11 20 12 21 13 22 14 23 15 24 16 25 17 26 18 COM9 COM16
(After Shift Right)
Figure 9. 1-line x 26ch. Display with 40 SEG. Extension Driver (6-dot Font Width)
16
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
(2) 6-dot 2-line Display In case of 2 line display with 6-dot font, the address range of DDRAM is 00H - 27H, 40H - 67H. (refer to Figure 10) When EXT = "High", extension driver will be used. Figure 11 shows the example that 40 segment extension driver is added.
1 COM1 COM8 COM17 COM24 00 40 SEG1 1 COM1 COM8 COM17 COM24 01 41
2 01 41
3 02 42
4 03 43
5 04 44
6 05 45
7 06 46
8 07 47
9 08 48
10 09 49
11 0A 4A
12 0B 4B
13 0C 4C
14 0D 4D
15 0E 4E
16 0F 4F
17 10 50
S6A0073 2 02 42 3 03 43 4 04 44 5 05 45 6 06 46 7 07 47 8 08 48
SEG60 9 09 49 10 0A 4A
SEG1 11 0B 4B 12 0C 4C 13 0D 4D 14 0E 4E
S6A0073 15 0F 4F 16 10 50 17 11 51
Display position 18 19 20 COM9 11 12 13 COM16 COM25 51 52 53 COM32 SEG60 DDRAM Address 18 12 52 19 13 53 20 14 54 COM9 COM16 COM25 COM32
(After Shift Left) 1 COM1 COM8 COM17 COM24 (After Shift Right) 27 67 2 00 40 3 01 41 4 02 42 5 03 43 6 04 44 7 05 45 8 06 46 9 07 47 10 08 48 11 09 49 12 0A 4A 13 0B 4B 14 0C 4C 15 0D 4D 16 0E 4E 17 0F 4F 18 10 50 19 11 51 20 12 52 COM9 COM16 COM25 COM32
Figure 10. 2-line x 20ch. Display (6-dot Font Width)
1 COM1 COM8 COM17 COM24 00 40 SEG1 1 COM1 COM8 COM17 COM24 01 41
2 01 41
3 02 42
4 03 43
5 04 44
6 05 45
7 06 46
8 07 47
9 08 48
10 09 49
11 0A 4A SEG1 11 0B 4B
12 0B 4B
13 0C 4C
14 0D 4D
15 0E 4E
16 0F 4F
17 10 50
18 11 51
19 12 52
20 13 53
21 14 54 SEG1 21 15 55
22 15 55
23 16 56
24 17 57
25 18 58
26 19 59 COM9 COM16 COM25 COM32
S6A0073 2 02 42 3 03 43 4 04 44 5 05 45 6 06 46 7 07 47 8 08 48
SEG60 9 09 49 10 0A 4A
S6A0073 12 0C 4C 13 0D 4D 14 0E 4E 15 0F 4F 16 10 50 17 11 51 18 12 52
SEG60 19 13 53 20 14 54
SEG36 22 16 56 23 17 57 24 18 58 25 19 59 26 1A 5A COM9 COM16 COM25 COM32
Extension Driver (40SEG)
(After Shift Left) 1 COM1 COM8 COM17 COM24 27 67 2 00 40 3 01 41 4 02 42 5 03 43 6 04 44 7 05 45 8 06 46 9 07 47 10 08 48 11 09 49 12 0A 4A 13 0B 4B 14 0C 4C 15 0D 4D 16 0E 4E 17 0F 4F 18 10 50 19 11 51 20 12 52 21 13 53 22 14 54 23 15 55 24 16 56 25 17 57 26 18 58 COM9 COM16 COM25 COM32 (After Shift Right)
Figure 11. 2-line x 26ch. Display with 40 SEG. Extension Driver (6-dot Font Width)
17
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(3) 6-dot 4-line Display In case of 4 line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H (refer to Figure 12). When EXT = "High", extension driver will be used. Figure 13 shows the example that 40 segment extension driver is added.
1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 00 20 40 60
2 01 21 41 61
3 02 22 42 62
4 03 23 43 63
5 04 24 44 64
6 05 25 45 65
7 06 26 46 66
8 07 27 47 67
9 08 28 48 68
10 09 29 49 69
Display position DDRAM Address
SEG1 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 01 21 41 61 2 02 22 42 62 3 03 23 43 63 4 04 24 44 64
S6A0073 5 05 25 45 65 6 06 26 46 66 7 07 27 47 67 8 08 28 48 68
SEG60 9 09 29 49 69 10 0A 2A 4A 6A
(After Shift Left) 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 13 33 53 73 2 00 20 40 60 3 01 21 41 61 4 02 22 42 62 5 03 23 43 63 6 04 24 44 64 7 05 25 45 65 8 06 26 46 66 9 07 27 47 67 10 08 28 48 68
(After Shift Right)
Figure 12. 4-line x 10 ch. Display (6-dot Font Width)
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 00 20 40 60 SEG1
2 01 21 41 61
3 02 22 42 62
4 03 23 43 63
5 04 24 44 64
6 05 25 45 65
7 06 26 46 66
8 07 27 47 67
9 08 28 48 68
10 09 29 49 69
11 0A 2A 4A 6A SEG1
12 0B 2B 4B 6B
13 0C 2C 4C 6C
14 0D 2D 4D 6D
15 0E 2E 4E 6E
16 0F 2F 4F 6F
Display position DDRAM Address
S6A0073
SEG60
SEG36 Extension Driver (40SEG)
1 COM1 COM8 COM16 COM17 COM24 COM25 COM32 01 21 41 61
2 02 22 42 62
3 03 23 43 63
4 04 24 44 64
5 05 25 45 65
6 06 26 46 66
7 07 27 47 67
8 08 28 48 68
9 09 29 49 69
10 0A 2A 4A 6A
11 0B 2B 4B 6B
12 0C 2C 4C 6C
13 0D 2D 4D 6D
14 0E 2E 4E 6E
15 0F 2F 4F 6F
16 10 30 50 70
(After Shift Left) 1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 13 33 53 73 2 00 20 40 60 3 01 21 41 61 4 02 22 42 62 5 03 23 43 63 6 04 24 44 64 7 05 25 45 65 8 06 26 46 66 9 07 27 47 67 10 08 28 48 68 11 09 29 49 69 12 0A 2A 4A 6A 13 0B 2B 4B 6B 14 0C 2C 4C 6C 15 0D 2D 4D 6D 16 0E 2E 4E 6E
(After Shift Right)
Figure 13. 4-line x 16ch. Display with 40 SEG. Driver (6-dot Font Width)
19
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations. Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0-DB6 ports. Cursor/Blink Control Circuit It controls cursor/blink ON/OFF and black/white inversion at cursor position. LCD Driver Circuit LCD Driver circuit has 34 common and 60 segment signals for LCD driving. Data from SEGRAM/CGRAM/CGROM is transferred to 60-bit segment latch serially, which is then stored to a 60-bit shift latch. When each com is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment latch. In case of 1-line display mode, COM0 - COM17 have a 1/17 duty ratio, and in 2-line or 4-line mode, COM0-COM33 have a 1/33 duty ratio.
20
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
CGROM (Character Generator ROM) CGROM has 5 x 8-dot 240 character pattern. CGRAM (Character Generator RAM) CGRAM has up to 5 x 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used (refer to Table 4). Table 4. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) 1) 5 x 8 dots Character Pattern
Character Code (DDRAM data) CGRAM Address CGRAM Data D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 1 1 1 1 . . 0 0 0 0 x 1 1 1 1 . . 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 . . 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B1 B0 x 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 B1 B0 x 0 1 1 1 1 1 1 0 . . 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0
Pattern Number Pattern 1
. . . . .
. . . . .
. . . . .
. . Pattern 8
. . . . .
. . . . .
. . . . .
21
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
2) 6 x 8 dots Character Pattern
Character Code (DDRAM data) 0 0 0 0 x 0 0 0 0
CGRAM Address 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 . . 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B1 B0 0 1 0 1 0 1 0 1 . . . . . B1 B0
CGRAM Data 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 . . 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
Pattern Number Pattern 1
. . . . .
. . . . .
. . 0 0 0 0 x 1 1 1 1
. . 1
. . Pattern 8
. . . . .
. . . . .
. . . . .
NOTES: 1. When Be(Blink Enable bit) = "High", blink is controlled by B1 and B0 bit. In case of 5-dot font width, when B1 = "1", enabled dots of P0 - P4 will blink, and when B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and B0 = " 0", blink will not happen. In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen. 2. "X" : don't care
22
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
SEGRAM (Segment Icon RAM) SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0(COM17) makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0(COM33) does that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8). Table 5. Relationship between SEGRAM Address and Display Pattern SEGRAM Address
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 D6 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 D5 X X X X X X X X X X X X X X X X D4 S1 S6 S11 S16 S21 S26 S31 S36 S41 S46 S51 S56 S61 S66 S71 S76 D3 S2 S7 S12 S17 S22 S27 S32 S37 S42 S47 S52 S57 S62 S67 S72 S77
SEGRAM Data Display Pattern 5-dot Font Width
D2 S3 S8 S13 S18 S23 S28 S33 S38 S43 S48 S53 S58 S63 S68 S73 S78 D1 S4 S9 D0 S5 S10 D7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 D6 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0
6-dot Font Width
D5 S1 S7 S13 S19 S25 S31 S37 S43 S49 S55 S61 S67 S73 S79 S85 S91 D4 S2 S8 S14 S20 S26 S32 S38 S44 S50 S56 S62 S68 S74 S80 S86 S92 D3 S3 S9 S15 S21 S27 S33 S39 S45 S51 S57 S63 S69 S75 S81 S87 S93 D2 S4 S10 S16 S22 S28 S34 S40 S46 S52 S58 S64 S70 S76 S82 S88 S94 D1 S5 S11 S17 S23 S29 S35 S41 S47 S53 S59 S65 S71 S77 S83 S89 S95 D0 S6 S12 S18 S24 S30 S36 S42 S48 S54 S60 S66 S72 S78 S84 S90 S96
S14 S15 S19 S20 S24 S25 S29 S30 S34 S35 S39 S40 S44 S45 S49 S50 S54 S55 S59 S60 S64 S65 S69 S70 S74 S75 S79 S80
NOTES: 1. B1, B0 : Blinking control bit
Control Bit BE 0 1 1 1
2. 3.
Blinking Port B0 X 0 1 X 5-dot font width No blink No blink D4 D4 - D0 6-dot font width No blink No blink D5 D5 - D0
B1 X 0 0 1
S1 - S80 : Icon pattern ON/OFF in 5-dot font width S1 - S96 : Icon pattern ON/OFF in 6-dot font width "X" : don't care
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S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-Dot Font Width (FW = 0)
S1
S2
S3
S4
S5
S6
S7
S8
S9 S10
S11 S12 S13 S14 S15
S56 S57 S58 S59 S60
S61 S62 S63 S64 S65
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64 SEG65
...
Extension Driver 6-Dot Font Width (FW = 1)
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18
S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
...
Extension Driver
Figure 14. Relationship between SEGRAM and Segment Display
24
SEG66
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG65
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
INSTRUCTION DESCRIPTION
OUTLINE To overcome the speed difference between internal clock of S6A0073 and MPU clock, S6A0073 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. Instruction can be divided largely four kinds, (1) S6A0073 function set instructions ( set display methods, set data length, etc.) (2) address set instructions to internal RAM (3) data transfer instructions with internal RAM (4) others . The address of internal RAM is automatically increased or decreased by 1. When IE = "High", S6A0073 is operated according to Instruction Set 1 (Table 6) and when IE = "Low", S6A0073 is operated according to Instruction Set 2 (Table 10).
NOTE: During internal operation, Busy Flag (DB7) is read High. Busy Flag check must be preceded the next instruction. When an MPU program with Busy Flag (DB7) checking is made, 1/2 fOSC is necessary for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW".
25
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(1) INSTRUCTION DESCRIPTION 1 (IE = "HIGH") Table 6. Instruction Set 1
Instruction RE RS R/ W Clear display X 0 0 0 0 0 0 0 0 0 1 Write "20" to DDRAM, and set DDRAM address to "00H" from AC. Return home 0 0 0 0 0 0 0 0 0 1 x Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Power down mode 1 0 0 0 0 0 0 0 0 1 PD Set power down mode bit. (PD = "1" : power down mode set, PD = "0" : power down mode disable) Entry mode set 0 0 0 0 0 0 0 0 1 I/D S Assign cursor moving direction, 39s 39s 1.53ms 1.53ms
Instruction Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time (fosc=270kHz)
(I/D = "1": increment, I/D = "0": decrement, and display shift enable bit. (S = "1": make display shift of the enabled lines by the DS4DS1 bits in the shift Enable instruction S = "0": display shift disable)
1 0 0 0 0 0 0 0 1 1 B/D Segment bidirectional function. (BID = "1": Seg60 Seg1 BID = "0": Seg1 Seg60)
Display ON/OFF Control
0
0
0
0
0
0
0
1
D
C
B
Set display/cursor/blink on/off D = "1" : display on, D = "0" : display off, C = "1" : cursor on, C = "0" : cursor off, B = "1" : blink on, B = "0" : blink off. Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1" : 6-dot font width, FW = "0" : 5-dot font width, B/W = "1" : black/white inverting of cursor enable, B/W = "0" : black/white inverting of cursor disable. NW = "1" : 4-line display mode, NW = "0" : 1-line or 2-line display mode.
39s
Extended function set
1
0
0
0
0
0
0
1
FW B/W NW
39s
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
Table 6. Instruction Set 1 Continued
Instruction RE RS R/ W Cursor or Display Shift 0 0 0 0 0 0 1 S/C R/L X X Cursor or display shift. S/C = "1" : display shift, S/C = "0" : cursor shift, R/L = "1" : shift to right, R/L = "0" : shift to left. Shift Enable 1 0 0 0 0 0 1 DS4 DS3 DS2 DS1 (when DH = "1") Determine the line for display shift . DS1 = "1/0": 1st line display shift enable/disable DS2 = "1/0": 2nd line display shift enable/disable DS3 = "1/0": 3rd line display shift enable/disable DS4 = "1/0": 4th line display shift enable/disable. Scroll Enable 1 0 0 0 0 0 1 HS4 HS3 HS2 SH1 (when DH = "0") Determine the line for horizontal smooth scroll. HS1 = "1/0" : 1st line dot scroll enable/disable HS2 = "1/0" : 2nd line dot scroll enable/disable HS3 = "1/0" : 3rd line dot scroll enable/disable HS4 = "1/0" : 4th line dot scroll enable/disable. Function Set 0 0 0 0 0 1 DL N RE (0) DH RE V Set interface data length (DL = "1" : 8-bit, DL = "0" : 4-bit), numbers of display line when NW = "0", (N = "1" : 2-line, N = "0" : 1-line), extension register, RE("0"), shift/scroll enable DH = "1" : display shift enable DH = "0" : dot scroll enable. And reverse bit REV = "1" : reverse display, REV = "0" : normal display. 1 0 0 0 0 1 DL N RE (1) BE LP Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0" : CGRAM/SEGRAM blink enable/disable LP = "1" : low power mode LP = "0" : normal operation mode 39s 39s 39s 39s 39s
Instruction Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time (fosc=270kHz)
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S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Instruction Set 1 continued
Instruction RE RS R/ W Set CGRAM Address Set SEGRAM Address Set DDRAM Address Set Scroll Quantity Read Busy flag and Address x 0 1 BF 1 0 0 1 X SQ 5 SQ 4 SQ 3 SQ 2 SQ 1 SQ 0 0s Set the quantity of horizontal dot scroll. 39s 0 0 0 1 1 0 0 0 1 X X AC3 AC2 AC1 AC0 Set SEGRAM address in address counter. AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39s 39s 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39s
Instruction Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time (fosc=270kHz)
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = "1" : busy state, BF = "0" : ready state.
Write Data
X
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM (DDRAM / CGRAM / SEGRAM).
43s
Read Data
X
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM (DDRAM / CGRAM / SEGRAM).
43s
NOTE: When an MPU program with Busy Flag (DB7) checking is mode, 1/2 fOSC is necessary for executing the next instruction by the falling edge of the "E" signal after the Busy Flag (DB7) goes to "low". "X": Don't care
28
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
1) Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). 2) Return Home: (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. 3) Power Down Mode Set: (RE = 1) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 PD
Power down mode enable bit set instruction. When PD = "High", it makes S6A0073 suppress current consumption except the current needed for data storage by executing next three functions. * * * Make the output value of all the COM/SEG ports VDD Make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to "Low" Disable voltage converter to remove the current through the divide resistor of power supply.
This instruction can be used s power sleep mode. When PD = "Low", power down mode becomes disabled.
29
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
4) Entry Mode Set (1) RE = 0 RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Set the moving direction of cursor and display. I/D : Increment/decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM. When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the Shift Enable instruction is shifted to the right (I/D = "0") or to the left(I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display as the above function is not performed. (2) RE = 1 RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 BID
Set the data shift direction of segment in the application set. BID : Data Shift Direction of Segment When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG100. When BID = "High", segment data shift direction is set to reversely from SEG100 to SEG1. By using this instruction, the efficiency of application board area can be raised. * The BID setting instruction is recommended to be set at the same time level of function set instruction. * DB1 bit must be set to "1".
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
5) Display ON/OFF Control ( RE = 0 ) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has frequency of 270kHz, blinking has 370 ms interval. When B = "Low", blink is off. 6) Extended Function Set ( RE = 1 ) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 F/W DB1 B/W DB0 NW
FW : Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit0,including the left most space bit of CGRAM.(refer to Figure 15) When FW = "Low", 5-dot font width is set. B/W : Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has 370 ms intervals. NW : 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition.
6-bit S p a c e CGROM Characte Font (5-dot) CGROM
6-bit CGRAM Characte Font (6-dot) CGRAM
8-bit
8-bit
Figure 15. 6-dot Font Width CGROM/CGRAM
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7) Cursor or Display Shift (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 DB0 -
Shift right/left cursor position or display without writing or reading of display data. This instruction is used to correct or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note that display shift is performed simultaneously in all the line enabled by DS1 - DS4 in the Shift Enable instruction. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. During low power consumption mode, display shift may not be performed normally. Table 7. Shift Patterns according to S/C and R/L Bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, ADDRESS COUNTER is decreased by 1 Shift cursor to the right, ADDRESS COUNTER is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
8) Shift/Scroll Enable (RE = 1) (1) DH = 0 RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 HS4 DB2 HS3 DB1 HS2 DB0 HS1
HS : Horizontal Scroll per Line Enable. This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8) (2) DH = 1 RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 DS4 DB2 DS3 DB1 DS2 DB0 DS1
DS : Display Shift per Line Enable. This instruction selects shifting line to be shifted according to each line mode in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each line. If you set DS1 and DS2 to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to DS4) are set to "Low" (disable), no display is shifted.
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Table 8. Relationship between DS and COM signal Enable bit HS1/DS1 HS2/DS2 HS3/DS3 HS4/DS4 Enabled common signal during shift COM1 - COM8 COM9 - COM16 COM17 - COM24 COM25 - COM32 The part of display line that corresponds to enabled common signal can be shifted. Description
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9) Function Set (1) RE = 0 RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 RE(0) DB1 DH DB0 REV
DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it needs to transfer 4-bit data by two times. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit At this instruction, RE must be "Low". DH : Display shift enable selection bit. When DH = "High", enables display shift per line. When DH = "Low", enables smooth dot scroll. This bit can be accessed only when IE pin input is "High". REV : Reverse enable bit When REV = "High", all the display data are reversed. i.e., all the white dots become black and black dots become white. When REV = "Low", the display mode set normal display.
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(2) RE = 1 RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 RE(0) DB1 DH DB0 REV
DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it is required to transfer 4-bit data by two times. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits of shift/scroll enable instruction and BE bits of function set register can be accessed. BE : CGRAM/SEGRAM data blink enable bit BE = "High", makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM. LP : Low power consumption mode enable bit When EXT input is "Low"(without extension driver) and LP bit is set to "High", S6A0073 operates in low power consumption mode. During 1-line mode S6A0073 operates on a 4-division clock, and in 2-line or 4-line mode it operates on a 2division clock. According to this instruction, execution time becomes 4 or 2 times longer. Note not to use display shift instruction, as it may result incorrect operation. And the frame frequency is lower to 5/6 times lower than that of normal operation.
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10) Set CGRAM Address (RE = 0) RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 11) Set SEGRAM Address (RE = 1) RS 0 R/W 0 DB7 0 DB6 1 DB5 X DB4 X DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU. 12) Set DDRAM Address (RE = 0) RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H" in the 4th line. 13) Set Scroll Quantity (RE = 1) RS 0 R/W 0 DB7 1 DB6 X DB5 SQ5 DB4 SQ4 DB3 SQ3 DB2 SQ2 DB1 SQ1 DB0 SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (refer to Table 9). In this case S6A0073 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots. Table 9. Scroll Quantity According to HDS bits SQ5 0 0 0 0 : 1 1 SQ4 0 0 0 0 : 0 1 SQ3 0 0 0 0 : 1 X SQ2 0 0 0 0 : 1 X SQ1 0 0 1 1 : 1 X SQ0 0 1 0 1 : 1 X Function No shift shift left by 1-dot shift left by 2-dot shift left by 3-dot : shift left by 47-dot shift left by 48-dot
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14) Read Busy Flag & Address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0073 is in internal operation or not. If the resultant BF is High, the internal operation is in progress and should wait until BF to be Low, which by then the next instruction can be performed. In this instruction the value of address can also be read. 15) Write Data to RAM RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 16) Read Data from RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, as the direction of AC is not determined. If RAM data read several times without RAM address set instruction before read operation, the correct RAM data can be obtained from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, AC is increased/decreased by 1 like read operation after this. In this time, AC indicates the next address position, but the previous data can only be read by instruction.
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(2) INSTRUCTION DESCRIPTION 2 (IE = "LOW") Table 10. Instruction Set 2
Instruction RE RS R/ W Clear Display X 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM. and set DRAM address to "00H" from AC. Return Home X 0 0 0 0 0 0 0 0 1 X Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Entry Mode Set X 0 0 0 0 0 0 0 1 I/D S Assign cursor moving direction. I/D = "1" : increment, I/D = "0" : decrement. and display shift enable bit. S = "1" :make entire display shift of all lines during DDRAM write, S = "0":display shift disable Display ON/OFF Control 0 0 0 0 0 0 0 1 D C B Set display/cursor/blink on/off D = "1" : display on, D = "0" : display off, C = "1" : cursor on, C = "0" : cursor off, B = "1" : blink on, B = "0" : blink off. Extended function set 1 0 0 0 0 0 0 1 FW BW NW Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1" : 6-dot font width, FW = "0" : 5-dot font width, B/W = "1" : black/white inverting of cursor enable, B/W = "0" : black/white inverting of cursor disable NW = "1" : 4-line display mode, NW = "0" : 1-line or 2-line display mode Cursor or Display Shift 0 0 0 00 0 0 1 S/C R/L X X Cursor or display shift. S/C = "1" : display shift, S/C = "0" : cursor shift, R/L = "1" : shift to right, R/L = "0" : shift to left 39s 39s 39s 39s 1.53ms 1.53ms
Instruction Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time (fosc=270kHz)
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Table 10. Instruction Set 2 (continued)
Instruction RE RS R/ W Scroll Enable 1 1 HS4 HS3 HS2 HS1 Determine the line for horizontal smooth scroll. HS1 = "1/0" : 1st line dot scroll enable/disable HS2 = "1/0" : 2nd line dot scroll enable/disable HS3 = "1/0" : 3rd line dot scroll enable/disable HS4 = "1/0" : 4th line dot scroll enable/disable Function Set 0 1 DL N RE (0) X X Set interface data length DL = "1" : 8-bit, DL = "0" : 4-bit numbers of display line when NW = "0", N = "1" : 2-line, N = "0" : 1-line extension register, RE("0"), 1 1 DL N RE (1) BE LP Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0" : CGRAM/SEGRAM blink enable/disable LP = "1" : low power mode LP = "0" : normal operation mode Set CGRAM Address Set SEGRAM Address 1 0 0 0 1 X X AC3 AC2 AC1 AC0 Set SEGRAM address in address counter. 39s 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39s 39s 39s 39s
Instruction Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time (fosc=270kHz)
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Table 10. Instruction Set 2 (continued)
Instruction RE RS R/ W Set DDRAM Address Set Scroll Quantinty Read Busy flag and Address X 0 1 BF 1 1 X SQ 5 SQ 4 SQ 3 SQ 2 SQ 1 SQ 1 0s Set the quantity of horizontal dot scroll. 39s 0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39s
Instruction Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time (fosc=270kHz)
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = "1" : busy state, BF = "0" : ready state.
Write Data
X
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM (DDRAM / CGRAM / SEGRAM).
43s
Read Data
X
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM (DDRAM / CGRAM / SEGRAM).
43s
NOTE: When an MPU program with Busy Flag (DB7) checking is made, 1/2 fOSC (is necessary) for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "low".
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1) Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. And entry mode is set to increment mode (I/D = "1"). 2) Return Home RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. 3) Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM. When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "low") or to the left(I/D = "high"). But it will seem as if the cursor is not moving. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of entire display is not performed.
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4) Display ON/OFF Control ( RE = 0 ) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register preserves its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270kHz frequency, blinking has 370ms interval. When B = "Low", blink is off. 5) Extended Function Set ( RE = 1 ) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 FW DB1 BW DB0 NW
FW : Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit0,including the leftmost space bit of CGRAM.(refer to Figure 16). When FW = "Low", 5-dot font width is set. B/W : Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has 370ms intervals. NW : 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition.
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6-bit S p a c e CGROM Characte Font (5-dot) CGROM
6-bit CGRAM Characte Font (6-dot) CGRAM
8-bit
8-bit
Figure 16. 6-dot Font Width CGROM/CGRAM 6) Cursor or Display Shift (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 SC DB2 R/L DB1 DB0 -
Shift right/left cursor position or display without writing or reading of display data. This instruction is used to correct or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. Table 11. Shift Patterns According to S/C and R/L bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, ADDRESS COUNTER is decreased by 1 Shift cursor to the right, ADDRESS COUNTER is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
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7) Scroll Enable (RE = 1) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 HS4 DB2 HS3 DB1 HS2 DB0 HS1
HS : Horizontal Scroll per Line Enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set HS1 and HS2 to "high". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "high". (Refer to table 8) 8) Function Set (1) RE = 0 RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 RE(0) DB1 DB0 -
DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it is required to transfer 4-bit data twice. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit At this instruction, RE must be "Low".
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(2) RE = 1 RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 RE(1) DB1 RE DB0 LP
DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it is required to transfer 4-bit data twice. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll enable instruction and BE bits of function set register can be accessed. BE : CGRAM/SEGRAM data blink enable bit BE = "High", makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM. LP : Low power consumption mode enable bit When EXT port input is "Low"(without extension driver) and LP bit is set to "High", S6A0073 operates in low power consumption mode. During 1-line mode S6A0073 operates on a 4-division clock, and in 2-line or 4-line mode it operates on a 2division clock. According to this instruction, execution time becomes 4 or 2 times longer. Note not to use display shift instruction, it may happen wrong operation. And the frame frequency is lower to 5/6 than that of normal operation. 9) Set CGRAM Address (RE = 0) RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
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10) Set SEGRAM Address (RE = 1) RS 0 R/W 0 DB7 0 DB6 1 DB5 X DB4 X DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU. 11) Set DDRAM Address (RE = 0) RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H" in the 4th line. 12) Set Scroll Quantity (RE = 1) RS 0 R/W 0 DB7 1 DB6 X DB5 SQ5 DB4 SQ4 DB3 SQ3 DB2 SQ2 DB1 SQ1 DB0 SQ0
Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (refer to Table 12). In this case S6A0073 execute dot smooth scroll from 1 to 48 dots. Table 12. Scroll Quantity According to HDS bits
SQ5 0 0 0 0 : 1 1
SQ4 0 0 0 0 : 0 1
SQ3 0 0 0 0 : 1 X
SQ2 0 0 0 0 : 1 X
SQ1 0 0 1 1 : 1 X
SQ0 0 1 0 1 : 1 X
Function No shift shift left by 1-dot shift left by 2-dot shift left by 3-dot : shift left by 47-dot shift left by 48-dot
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13) Read Busy Flag & Address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0073 is in internal operation or not. If the resultant BF is High, the internal operation is in progress and should wait until BF becomes "LOW", which by then the next instruction can be performed. In this instruction value of address counter can also be read. 14) Write data to RAM RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 15) Read data from RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If the RAM data several is read times without RAM address set instruction before read operation, the correct RAM data from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this AC is increased/decreased by 1 as in read operation after this. In this time, AC indicates the next address position, but the previous data can only be read by read instruction.
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INTERFACE WITH MPU S6A0073 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. Hence, both types 4 or 8-bit MPU can be used. In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data. (1) When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two times. Busy Flag outputs "High" after the second transfer are ended. (2) When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7. (3) If IM is set to "Low", serial transfer mode is set.
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INTERFACE WITH MPU IN BUS MODE 1) Interface with 8-bits MPU If 8-bits MPU is used, S6A0073 can connect directly with that. In this case, port E, RS, R/W and DB0 to DB7 need to interface each other. Example of timing sequence is shown below.
RS R/W
E Internal signal DB7 DATA
Internal Operation No Busy
Busy
Busy
DATA
Instruction
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction
Figure 17. Example of 8-bit Bus Mode Timing Sequence 2) Interface with 4-bits MPU If 4-bits MPU is used, S6A0073 can connect directly with this. In this case, E, RS, R/W and DB4 to DB7 need to interface each other. The transfer is performed by twice. Example of timing sequence is shown below.
RS R/W
E Internal signal
Internal Operation No Busy
DB7
D7
D3
Busy
AC3
AC3
D7
D3
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Fig 18. Example of 4-bit Bus Mode Timing Sequence
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Interface with MPU in Serial Mode When IM input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing transfer clock), SID (serial input data), and SOD (serial output data), are used. If S6A0073 is to be used with other chips, chip select port (CS) can be used. By setting CS to "Low", S6A0073 can receive SCLK input. If CS is set to "High", S6A0073 reset the internal transfer counter. Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, register read write control bit (R/W), register selection bit (RS) and end bit that indicates the end of start byte. Whenever succeeding 5 "High" bits are detected by S6A0073, it resets the serial transfer counter and prepares to receive next information. The next input data is the register selection bit which determines which register will be used, and read write control bit that determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of start byte. (refer to Figure 19, Figure 20) (1) Write Operation (R/W = 0) After start byte is transferred from MPU to S6A0073, 8-bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. To transfer several bytes continuously without changing RS bit and RW bit, start byte transfer is needed only at first starting time, I, e, after first start byte is transferred, real data succeeding can be transferred. (2) Read Operation (R/W = 1) After start byte is transferred to S6A0073, MPU can receive 8-bit data through the SOD at a time from the LSB. Waiting time is needed to insert between start byte and data reading, as internal reading from RAM requires some delay. Continuous data reading is possible such as serial write operation. It also needs only one start bytes, only if some delay between reading operations of each byte is inserted. During the reading operation, S6A0073 observes succeeding 5 "High" from MPU. If it is detected, S6A0073 restarts serial operation at once and prepares to receive RS bit. So in continuous reading operation, SID port must be "low".
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Serial Write Operation CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK (Input) SID (Input)
1 1 1 1 1 R/WRS 0 D0 D1 D2 D3 0 0 0 0 D4 D5 D6 D7 0 0 0 0
Starting Byte Synchronizing Bit String Lower Data 1'st Byte
Instruction Upper Data
2'nd Byte
Serial Read Operation CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK (Input) SID (Input)
1 1 1 1 1 R/W RS 0 0 0 0 0 0 0 0 0
SOD (Output) Starting Byte
D0 D1 D2 D3 D4 D5 D6 D7
Busy Flag/ Read Data Lower Data Upper Data
Synchronizing Bit String
Figure 19. Timing Diagram of Serial Data Transfer
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34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Continuous Write Operation SCLK SID
Start Byte 1'st Byte 2'nd Byte
Wait
1'st Byte 2'nd Byte
Wait
1'st Byte 2'nd Byte
Instruction1
Instruction2 Instruction1 Execution Time
Instruction3 Instruction2 Execution Time
Instruction3 Execution Time
Continuous Read Operation SCLK SID SOD
Start Byte Data Read1 Data Read2 Data Read3
Wait
Wait
Wait
Instruction1 Execution Time
Instruction2 Execution Time
Instruction3 Execution Time
Fig 20. Timing Diagram of Continuous Data Transfer
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APPLICATION INFORMATION ACCORDING TO LCD PANEL
1) LCD Panel: 24 Character x 1-line Format (5-dot Font,1/17 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG58 SEG59 SEG60 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
S6A0073
2) LCD Panel: 24 Character x 2-line Format (5-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG58 SEG59 SEG60 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
S6A0073
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3) LCD Panel: 12 Character x 4-line Format (5-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG58 SEG59 SEG60
S6A0073
%
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4) LCD Panel: 10 Character x 4-line Format (6-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG58 SEG59 SEG60
S6A0073
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5) LCD Panel: 20 Character x 4-line Format (5-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32
S6A0073
VDD EXT
COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG58 SEG59 SEG60 SEG1 SEG2 SEG3 SEG4 SEG5 SEG36 SEG37 SEG38 SEG39 SEG40
Extension Driver
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INITIALIZING 1) Initializing by Internal Reset Circuit When the power is turned on, S6A0073 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. (1) Display Clear instruction Write "20H" to all DDRAM (2) Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode RE = 0 : Extension register disable BE = 0 : CGRAM/SEGRAM blink OFF LP = 0 : Operate in normal mode (Not in Low Power Mode) DH = 0 : Horizontal scroll enable REV = 0 : Normal display mode (Not reversed display) (3)Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF (4) Set Entry Mode instruction I/D = 1 : Increment by 1 S = 0 : No entire display shift BID = 0 : Normal direction segment port (5) Set Extension Function instruction FW = 0 : 5-dot font width character display B/W = 0 : Normal cursor (8th line) NW = 0 : Not 4-line display mode, 2-line mode is set because of N("1") (6) Enable Scroll/Shift instruction HS = 0000 : Scroll per line disable DS = 0000 : Shift per line disable (7) Set scroll Quantity instruction SQ = 000000 : Not scroll
2) Initializing by Hardware RESET input When RESET pin = "Low", S6A0073 can be initialized like the case of power on reset. During the power on reset operation, this pin is ignored.
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INITIALIZING BY INSTRUCTION 1) 8-bit Interface Mode
Power On
Wait for more than 20ms after DD rises to 4.5V V Wait for more than 30ms after DD rises to 2.7V V DL Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(1) DB3 N DB2 0 DB1 X DB0
Condition: fosc = 270kHz 0 1 0 X N 1 2-line mode 4-bit interface 8-bit interface 1-line mode
Wait for more than 39 s D
0 1
Display off Display on Cursor off Cursor on Blink off Blink on
Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 C B 1 0 B 1 0
Wait for more than 39 s
Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Wait for more than 1.53 s m 0 I/D Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 0 S S 1 Initialization End Entire shift on Entire shift off 1 Increment mode Decrement mode
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2) 4-bit Interface Mode
Power On
Wait for more than 20ms after V rises to 4.5V DD Wait for more than 30ms after V rises to 2.7V DD Condition: fosc = 270kHz Function Set DL RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 DL(0) DB3 X DB2 X DB1 X DB0 X 0 N Wait for more than 39 s 1 2-line mode 1-line mode 1 8-bit interface 0 4-bit interface
Function Set RS 0 0 R/W DB7 0 0 0 N DB6 0 0 DB5 1 X DB4 0 X DB3 X X DB2 X X DB1 X X DB0 X X
Wait for more than 39 s 0 D Display ON/OFF Control RS 0 0 R/W DB7 0 0 0 1 DB6 0 D DB5 0 C DB4 0 B DB3 X X DB2 X X DB1 X X DB0 0 X X 0 Wait for more than 39 s B 1 Blink on Blink off C 1 Cursor on Cursor off 1 Display on Display off
Clear Display RS 0 0 R/W DB7 0 0 0 0 DB6 0 0 DB5 0 0 DB4 0 1 DB3 X X DB2 X X DB1 X X DB0 X X
Wait for more than 1.53 ms
Entry Mode Set I/D RS 0 0 R/W DB7 0 0 0 0 DB6 0 1 DB5 0 I/D DB4 0 SH DB3 X X DB2 X X DB1 X X DB0 X
0 1 0 X SH 1
Decrement mode Increment mode Entire shift off Entire shift on
Initialization End
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EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE
1) IE = "Low"
1. Power supply on: Initialized by the internal power on reset circuit RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LCD DISPLAY
2. Function Set: 8-bit, 1-line, RE (0) RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 X DB0 X
3. Display ON/OFF Control: Display/Cursor on RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 1 DB1 1 DB0 _ 0
4. Entry Mode Set: Increment RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 _ 0
5. Write Data to DDRAM: Write S RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 S_ 1
6. Write Data to DDRAM: Write A RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 SA_ 1
7. Write Data to DDRAM: Write M RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 1 DB1 0 DB0 SAM_ 1
8. Write Data to DDRAM: Write S RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 SAMS_ 1
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9. Write Data to DDRAM: Write U RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LCD DISPLAY SAMSU_
0
0
1
0
1
0
1
0
1
10. Write Data to DDRAM: Write N RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMSUN_ 0 0 1 0 0 1 1 1 0
11. Write Data to DDRAM: Write G RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMSUNG_ 0 0 1 0 0 0 1 1 1
12. Cursor or Display Shift: Cursor shift to right RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMSUNG _ 0 0 0 0 1 0 1 X X
13. Entry Mode Set: Entire Display Shift Enable RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMSUNG _ 0 0 0 0 0 0 1 1 0
14. Write Data to DDRAM: Write K RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AMSUNG K_ 0 0 1 0 0 1 0 1 1
15. Write Data to DDRAM: Write S RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSUNG KS_ 0 0 1 0 1 0 0 1 1
16. Write Data to DDRAM: Write 0 RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SUNG KS0_ 0 0 0 1 1 0 0 0 0
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17. Write Data to DDRAM: Write 0 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 0 DB0
LCD DISPLAY UNG KS00_ 0
18. Write Data to DDRAM: Write 7 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 1 DB1 1 DB0 NG KS007_ 1
19. Write Data to DDRAM: Write 2 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 1 DB0 G KS0073_ 0
20. Cursor or Display Shift: Cursor shift left RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 0 DB1 x DB0 G KS0073 x
21. Write Data to DDRAM: Write 8 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 1 DB0 KS0073_ 1
22. Return Home RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 SAMSUNG KS0073 x
23. Clear Display RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 _ 1
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2) IE = "High"
1. Power Supply on: Initialized by the internal power on reset circuit RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
2. Function Set: 8-bit, RE(1) RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0
3. Extended Function Set: 5-font, 4-line RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 1
4. Function Set: RE(0) RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
5. Display ON/OFF Control: Display/Cursor on RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
_
6. Write Data to DDRAM: Write S RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1
S_
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7. Write Data to DDRAM: Write A RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
SA_
12. Write Data to DDRAM: Write G RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 1
SAMSUNG_
13. Set DDRAM Address 20H RS 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
SAMSUNG _
14. Write Data to DDRAM: Write K RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
SAMSUNG K_
19. Write Data to DDRAM: Write 3 RS 1 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 1 DB1 1 DB0 1
SAMSUNG KS0073_
20. Set DDRAM Address 40H RS 0 R/W 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
SAMSUNG KS0073 _
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21. Write Data to DDRAM: Write L RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 1 DB1 0 DB0 0
SAMSUNG KS0073 L_
30. Write Data to DDRAM: Write R RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 0
SAMSUNG KS0073 LCD DRIVER_
31. Set DDRAM Address 60H RS 0 R/W DB7 0 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
SAMSUNG KS0073 LCD DRIVER _
43. Write Data to DDRAM: Write R RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER_
44. Function Set: RE("0"), DH("1") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER_
45. Function Set: RE("1") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER_
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46. Shift/Scroll Enable: DS4("1"), DS3/2/1("0") RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER_
47. Function Set: RE("0") RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER_
48. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0073 LCD DRIVER CONTROLLER_
49. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0073 LCD DRIVER CONTROLLER_
50. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0073 LCD DRIVER ONTROLLER_
51. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0073 LCD DRIVER NTROLLER_
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52. Return Home RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 x
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
53. Function Set: RE("0), REV("1") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 1
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
54. Cursor or Display Shift: Display shift to right RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 1 DB1 x DB0 x
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
55. Cursor or Display Shift: Display shift to right RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 1 DB1 x DB0 x
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
56. Return Home RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 x
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
57. Function Set: RE("0"), REV("0") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
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58. Function Set: RE("1") RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0
SAMSUNG KS0073 LCD DRIVER & CONTROLLER
59. Entry Mode Set: BID("1") RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 1
60. Write Data to DDRAM: Write B RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
61. Write Data to DDRAM: Write I RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 1
62. Write Data to DDRAM: Write D RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
63. Clear Display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 _
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FRAME FREQUENCY 1) 1/17 Duty Cycle
1-line selection period 1 VDD V1 COM1 V4 V5 1 Frame 1 Frame .. 2 3 4 ... 16 17 1 2 3 ... 16 17
Item 1-line selection period Frame frequency
Normal Display Mode (LP = 0) 5-dot font width 200 clocks 79.4Hz 6-dot font width 240 clocks 66.2Hz
Item 1-line selection period Frame frequency 60 clocks 66.2Hz
Low Power Mode (LP = 1) 5-dot font width 6-dot font width 72 clocks 55.1Hz
* fosc = 270kHz (1 clock = 3.7s)
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2) 1/33 Duty Cycle
1-line selection period 1 VDD V1 COM1 V4 V5 1 Frame 1 Frame .. 2 3 4 ... 32 33 1 2 3 ... 32 33
Item 1-line selection period Frame frequency
Normal Display Mode (LP = 0) 5-dot font width 100 clocks 81.8Hz 6-dot font width 120 clocks 68.2Hz
Item 1-line selection period Frame frequency
Normal Display Mode (LP = 1) 5-dot font width 60 clocks 68.2Hz 6-dot font width 72 clocks 56.8Hz
O fosc = 270kHz (1 clock = 3.7s)
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POWER SUPPLY FOR DRIVING LCD PANEL
1) When an external power supply is used
VDD
R R R0 R R
VDD V1 V2 V3 V4 V5
VEE
2) When an internal booster is used
Boosting Twice VDD + 1 F + VCI GND C1 C2 V5OUT2 V5OUT3 VDD V1 V2 V3 V4 V5 R R R0 R R 1 F + 1 F + VDD + 1 F +
Boosting Three Times
VCI GND C1 C2 V5OUT2 V5OUT3
VDD V1 V2 V3 V4 V5
R R R0 R R
1 F +
Can be detached if not using power down mode
Can be detached if not using power down mode
NOTES: 1. Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage. Especially, a voltage of over 4.3V should not be input to the reference voltage(Vci) when boosting three times. 2. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice. 3. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (Refer to Table 13)
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Table 13. Duty Ratio and Power Supply for LCD Driving Item Number of lines Duty ratio Bias Divided resistance R R0 1 1/17 1/5 R R Data 2 or 4 1/33 1/6.7 R 2.7R
MAXIMUM ABSOLUTE RATE
Characteristic Power Supply Voltage (1) Power Supply Voltage (2) Input Voltage Operating Temperature Storage Temperature Symbol VDD VLCD VIN TOPR TSTG Value -0.3 to +7.0 VDD -15.0 to VDD +0.3 -0.3 to VDD +0.3 -30 to +80 -55 to +125 UNIT V V V C C
O Voltage greater than above may damage to the circuit (VDD V1 V2 V3 V4 V5)
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ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 2.7V to 5.5V, Ta = -30 to +85C) Characteristic
Operating Voltage Supply Current
Symbol
VDD IDD
Condition
Internal oscillation or external clock. (VDD=3.0V, fOSC = 270kHz) VDD = 2.7 to 3.0 VDD = 3.0 to 5.5
Min
2.7 -
Typ
0.15
Max
5.5 0.3
Unit
V mA
Input Voltage (1) (except OSC1)
VIH1 VIL1
0.7VDD -0.3 -0.3 0.7VDD 0.75VDD 0.8VDD -
-50 270 270 50 -4.2 -5.1 -
VDD 0.2VDD 0.6 VDD 0.2VDD 0.2VDD 0.2VDD 1 1 1 -120 350 410 55 0.2 4.5 13.0 13.0 V kHz kHz % s V A V V V V V
Input Voltage (2) (OSC1) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (expect DB0 to DB7) Voltage Drop
VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM vdSEG IOH = -0.1mA IOL = 0.1mA IO = -40A IO = 40A IO = 0.1mA
-
Input Leakage Current Low Input Current Internal Clock (external Rf)
IIL IIN fOSC fEC
VIN = 0V to VDD VIN = 0V, VDD = 3V (pull up) Rf = 91k 2% (VDD = 5V)
-1 -10 190 125
External Clock
Duty t R, t F
-
45 -
Voltage Converter Out2 (Vci = 4.5V) Voltage Converter Out3 (Vci = 2.7V) Voltage Converter Input LCD Driving Voltage
VOUT2 VOUT3 Vci VLCD
Ta = 25C, C = 1F, IOUT = 0.25mA, fOSC = 270kHz VDD-V5 1/5 bias 1/6.7 bias
-3.0 -4.3 2.5 3.0 3.0
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S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
AC Characteristics (VDD = 4.5 to 5.5V, Ta = -30 to +85C) Mode E Cycle Time E Rise / Fall Time (1) Write Mode E Pulse Width (High, Low) Item Symbol tC t R, t F tW tSU1 tH1 tSU2 tH2 tC t R, t F tW tSU tH tD tDH tC tR,tF tW tSU1 tH1 tSU2 tH2 tD tDH Min 500 230 40 10 60 10 500 230 40 10 5 0.5 200 60 20 100 100 5 Typ Max 20 20 160 20 50 160 ns s ns ns Unit
( refer to Figure 21) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time (2) Read Mode (refer to Figure 22) E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise / Fall Time Serial Clock Width (High, Low) (3) Serial Interface Mode (refer to Figure 23) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time
74
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
AC Characteristics (Continued) (VDD = 2.7 to 4.5V, Ta = -30 to +85C) Mode E Cycle Time E Rise / Fall Time (4) Write Mode E Pulse Width (High, Low) Item Symbol tC t R, t F tW tSU1 tH1 tSU2 tH2 tC t R, t F tW tSU tH tD tDH tC tR,tF tW tSU1 tH1 tSU2 tH2 tD tDH Min 1000 450 60 20 195 10 1000 450 60 20 5 1 400 60 20 200 200 5 Typ Max 25 25 360 20 50 360 ns s ns ns Unit
( refer to Figure 21) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time (5) Read Mode (refer to Figure 22) E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise / Fall Time Serial Clock Width (High, Low) (6) Serial Interface Mode (refer to Figure 23) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time
75
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
AC Characteristics (Continued) (VDD = 2.7 to 5.5V, Ta = -30 to + 85C) Mode Item Clock Pulse Width (High, Low) (7) Interface Mode with Extension Driver (refer to Figure 24) Clock Rise / Fall Time Clock Setup Time Data Setup Time Data Hold Time M Delay Time Symbol tW t R, t F tSU1 tSU2 tDH tDM Min 800 500 300 300 -1000 Typ Max 100 1000 ns Unit
RS
VIH1 VIL1 tsu1 VIL1 tw
th1 VIL1 th1 tf VIH1 VIL1 tsu2 Valid Data tc
R/W
E tr DB0 - DB7
VIH1 VIL1 VIH1 VIL1
th2 VIH1 VIL1
VIL1
Figure 21. Write Mode
76
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0073
RS
VIH1 VIL1 tsu VIH1 tw
th VIH1 th tf VIH1 VIL1 tD VIH1 VIL1 tDH VIH1 VIL1
R/W
E tr DB0 - DB7
VIH1 VIL1
VIL1
Valid Data tc
Figure 22. Read Mode
tC CS VIL1 tsu1 VIH1 VIL1 tsu2 SID tD SOD VOH1 VOL1 tDH tr tw tf VIH1VIH1 VIL1 VIL1 th2 VIH1 VIL1 tw VIL1 th1
SCLK
Figure 23. Serial Interface Mode
77
S6A0073
34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
tf CLK1 VOH2 tr CLK2 VOH2 VOL2 tSU1 D tSU1 M tDM VOL2 tDH VOH2 tw VOL2 tw VOH2 VOL2 tw VOH2 VOL2
Figure 24. Interface Mode with Extension Driver
RESET TIMING (VDD = 2.7 to 5.5V, Ta = -30 to +85C) Item Reset low level width (refer to Figure 25) Symbol tRES Min 10 Typ Max Unit ms
tRES RESET VIL1 VIL1
Figure 25. Reset Timing Diagram
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